Along with improvement of the performance of information processing devices, the data rate of data signals transmitted and received internally or externally of the devices is being increased.
Related techniques are disclosed in, for example, Japanese Laid-open Patent Publication Nos. 2016-072932 and 2015-084487, T. Shibasaki et al., “A 56 Gb/s NRZ-Electrical 247 mW/lane Serial-Link Transceiver in 28 nm CMOS,” in IEEE ISSCC Dig. Tech. Papers, February 2016, pp. 64-65, and S. Jalali et al., “An 8 mW Frequency Detector for 10 Gb/s Half-Rate CDR using Clock Phase Selection,” in IEEE Custom Integrated Circuits Conference (CICC), pp. 1-4, September 2013.